1. Field of the Invention
The invention applies to reading registers formed by means of a shift register of the charge-coupled device type and having an output stage mounted at least partially on one and the same semiconductor substrate as the shift register. The invention can be applied particularly in the case of shift registers working in a mode that is not two-phased, and it particularly concerns means designed to obtain a greater range in amplitude of the output signal for given supply voltages.
2. Description of the Prior Art
Reading registers of this type are commonly used in memory devices or delay lines or, again, for example in photosensitive sensors for cameras.
Charge-coupled devices are semiconductor-using systems wherein charges are stored in potential wells and wherein these charges are conveyed from one point to another by being transferred from one potential well to a neighboring potential well: the charges thus successively occupy all the potential wells between the zone of departure and the zone of arrival of these charges. In fact, the charges flow substantially on the surface of the semiconductor substrate or, possibly, in a shallow layer located near the surface (in a so-called "buried channel" device).
FIG. 1 gives a schematic and partial view of known type of reading register such as the one described above. This reading register is represented by a view in a section parallel to the direction in which the charges are transferred. This direction is symbolized in the figure by an arrow 2. The reading register is formed on a substrate 3 within, for example, P type doping. Near its surface 4, this substrate 3 may have a layer 5 with N type doping, in order to form a buried channel in a standard way. The reading register is formed by an shift register RD followed, in the direction of transfer of the charges, by an output circuit CS. The shift register includes a plurality of successive transfer stages, each having at least three electrodes. For the greater clarity of FIG. 1, a sequence of only three transfer stages, 6, 7, 8, has been shown, the last transfer stage 8 being in the vicinity of the output circuit CS, from which it is separated by an output electrode ES.
In the example shown by FIG. 1, the shift register RD is of the type working in four-phase mode in a standard way, that is, the transfer stages 6, 7, 8 each have, in the direction of transfer of the charges, a sequence of four electrodes E1, E2, E3, E4 made on top of the substrate 3. More precisely, these electrodes, as well as the output electrode ES, are made on top of an electrically insulating layer 9 which separates them from the N doped layer 5. The four electrodes E1 to E4 of each transfer stage are controlled by cyclical voltage pulses or transfer signals ST1, ST2, ST3, ST4 with different phases so as to generate, beneath these electrodes, potential barriers and potential wells to transfer the charges to the output circuit CS. The first, second, third and fourth transfer signals ST1, ST2, ST3, ST4 are applied respectively to all the first, second, third, fourth electrodes E1, E2, E3, E4.
The fourth electrode E4 of the transfer stage closest to the output circuit CS, namely the last transfer stage 8, forms the last electrode (according to the charge transfer direction 2) of the shift register RD, and it is followed by the output electrode ES to which a potential VES, a DC potential for example, is applied, making it possible to set up, in the output electrode ES, a potential barrier of separation between the potentials created beneath the last transfer stage 8 and an element for the terminal storage of the charges belonging to the output circuit CS. This element for the terminal storage of the charges is represented in the figure by zone 12 with N+type doping, that is, doping of the same type as that of the buried channel 5 but with more doping than this channel. This N+zone is inserted into the buried channel 5.
In fact, the junction between this N+doped zone 12 and the substrate 3, which has the opposite type of conductivity, i.e. it is P doped, sets up a diode 12a (symbolized in the figure by dashes) called a reading diode. When this diode 12a is reverse biased, it has a capacitance which provides for the storage of the charges in a standard way, and the reading diode 12a thus forms the above-mentioned terminal storage element.
Still in the charge transfer direction 2, we then find, above the substrate 3, a control gate GC which is itself followed by a second zone 13 with N+type doping, namely a zone of the same type as the buried channel 5, but with heavier doping than the latter: this second N+zone 13 is also inserted in the buried channel 5. In fact, the first N+doped zone 12, followed by a part 14 of the buried channel above which the control gate GC is placed, and the second N+doped zone 13 form a MOS type transistor, the zone 12 of which represents, for example, the source, the zone 13 of which represents the drain and the electrode GC of which represents the control gate. A DC supply voltage VDR of, for example +12 volts with respect to the potential of the substrate 3, is applied to the second zone 13 or drain and, furthermore, a resetting pulse SRN is applied to the control gate GC in order to make the MOS transistor conductive and, consequently, carry the first zone 12 to the potential of VDR. It does this at well-determined instants, outside which the potential of the first zone 12 (and hence the reading diode 12a) is floating and may therefore vary as a function of the accumulated charges. The reading diode 12a is connected to the input of an output amplifier 16 which receives a supply voltage V.sub.DD and delivers an output signal Ss, the value of which is a function of the quantity of charges present at the reading diode 12a.
FIGS. 2a to 2f illustrate the differences in phases among the transfer pulses or signals ST1 to ST4, and the relationship between these signals and the output signal Ss delivered by the output amplifier 16.
The transfer signals ST1 to ST4 are shown respectively in FIGS. 2a to 2d. These figures have one and the same shape, one and the same frequency but a different phase, and may have a state 0 or a state 1, the state 1 representing a positive potential with respect to the state 0. FIG. 2e represents the resetting pulses SRN which are applied to the control gate GC: these pulses vary also between a state 0 and a state 1 (which is positive with respect to the state 0). FIG. 2f illustrates the variations in amplitude of voltage VS of the output signal Ss which may vary, for example, between a maximum positive value +VSM corresponding to the value of the potential of VDR and a maximum negative value -VSM corresponding to a maximum quantity of charges on the reading diode 12a.
At the instant t0: the first transfer signal ST1, which is applied to the first electrodes E-, goes from the state 0 to the state 1. The second transfer signal ST2, applied to the second electrodes E2, is at the state 0. The third transfer signal ST3, applied to the third electrodes E3, is at the state 1. The fourth transfer signal ST4, applied to the fourth electrodes E4 is at the state 1; the resetting pulse SRN applied to the control electrode GC ends and goe from the state 1 to the state 0; the output signal Ss is at the value of +VSM, the reading diode having been connected to the potential VDR for the duration of the resetting pulse SRN
It should be noted that hereinafter only the states of the signals which have not been modified with respect to the above-mentioned instants are specified.
At the instant t1: the third transfer signal ST3 goes from the state 1 to the state 0. The output signal Ss has gone to a value Vst which is smaller than the value VSM and which represents a value of stabilization after the resetting operation. The reading diode, from this instant t1 onwards, is in principle ready to receive charges which will be expressed by a modification of the output signal Ss at output of the output amplifier 16. Assuming that, subsequently, no charge is transferred to the reading diode 12a, the output signal Sa preserves its stabilization value VST until the instant when a new resetting signal SRN starts.
At the instant t2: the second transfer signal ST2 goes from the state 0 to the state 1.
At the instant t3: the fourth transfer signal ST4 goes from the state 1 to the state 0.
At the instant t4: the third transfer signal ST3 goes from the state 0 to the state 1.
At the instant t5: the first transfer signal ST1 goes from the state 1 to the state 0.
At the instant t6: the fourth transfer signal ST4 goes from the state 0 to the state 1; a new resetting pulse starts; this pulse goes from the state 0 to the state 1; the output signal S tends from the value VST towards the value VSM.
At the instant t7 : the second transfer signal ST2 goes from the state 1 to the state 0; and the output signal Ss is at an intermediate level between the stabilization value VST and the maximum value VSM.
At the instant t8 : the first transfer signal STI goes from the state 0 to the state 1, and it is observed that the time between the instant t0 and the instant t8 corresponds to a full cycle of the first transfer signal ST1 and that this time corresponds to a time Tt for the transfer of charges from one stage to a following stage; the resetting signal Rn is completed and goes from the state 1 to the state 0. At this instant t8, the output signal Ss has recovered the value +VSM, following the resetting command, and tends towards the stabilization value VST.
At the instant t9: the third transfer signal ST3 goes from the state 1 to the state 0. It must be noted that this leads to the transferring, beneath the electrode E4, of the charges that were stored beneath the electrode E3. As a result, if the quantity of charges that were simultaneously contained beneath the electrode E3 and the electrode E4 were to be great, this transfer would have the consequence (as shall be further explained with reference to FIG. 3) of provoking an stray transfer of a part of these charges towards the reading diode 12a, the result of which is a negative variation of the output signal Ss which goes to a value VS1 below the stabilization value VST.
This brings out one of the major drawbacks of this operation in four-phase mode which, besides, has the advantage of providing for an efficient transfer of the charges owing to the presence, at the state ; (positive potential) of at least two neighboring electrodes. The drawback that has just been referred to lies in the fact that the operation just described leads to a disymmetry in the durations, firstly, of the time allocated to the resetting of the reading diode and, secondly, of the time allocated to the arrival of the charges at the reading diode. This drawback is particularly troublesome when the reading of the signal (corresponding to the charges transferred to the reading diode) is done by a method of double sampling or differential reading. For, in this case, the value of the useful signal at the output amplifier is given by the difference between the value read when all the charges have been transferred to the reading diode and the value present before the transfer of these charges, that is, theoretically, when the output signal Ss still has the value of the stabilization potential VST, which has a very short duration in this case.
At the instant t10: the second transfer signal ST2 goes from the state 0 to the state 1.
At the instant tll: the output signal Ss has the value VS1. The fourth transfer signal ST4, applied to all the fourth electrodes E4, goes from the state 1 to the state 0, namely to a more negative potential than that of the state 1. Assuming that the charges have been stored beneath the fourth electrode E4 of the first transfer stage, these charges are transferred to the reading diode 12a. This leads to a negative variation of the output signal Ss which goes from the value VSl to the value VS2 which is lower than VS1 and is close, for example, to the maximum negative value -VSM, and the difference between these two values represents the quantity of charges transferred to the reading diode 12a from the instant t11 onwards.
At the instant t12: the output signal Ss has reached the value VS2; the third transfer signal ST3 goes from the state 0 to the state 1.
At the instant t13, the first transfer signal ST1 goes from the state 1 to the state 0 (as earlier at the instant t5).
At the instant t14: the same signals are found again as at the instant t6: the fourth transfer signal ST4 applied to the fourth electrodes E4 goes from the state 0 to the state 1. The start of the resetting pulse SRN is found, that is, the potential applied to the control electrode GC goes from the state 0 to the state 1. A positive variation is noted in the output signal Ss which, starting from the value VS2, tends towards the value VS which is reached at the instant t15.
At the instant t16: the same events are found as at the instants t0 to t8 and a same subsequent operation is got as the one just described.
FIG. 3 shows the reading register RL in a sectional view similar to that of FIG. 2 but, in this figure, to simplify the description, the depiction of the shift register RD is restricted to the last transfer state 8, namely to the transfer stage closest to the output circuit CS. FIGS. 3a, 3b, 3c should be read with the FIG. 3, and illustrate the shapes of potentials VP set up beneath the different electrodes or gates and at the reading diode 12a. In accordance with the usual practice with respect to charge-coupled devices, the potentials are shown in increasing order downwards.
FIG. 3a shows the potentials VP set up in the substrate between the instant t8 and the instant t9. During this interval of time, the third and fourth transfer pulses ST3, ST4 are in the state 1 (the more positive potential) so that, beneath the third and fourth electrodes E3, E4, there is created a single potential well PU1, the depth of which corresponds to a potential VP1. At this instant, the second transfer pulse ST2 is at the state 0, the result of which, beneath the second electrode E2, is a potential VP2 that is negative with respect to the potential VP1 which is set u beneath the third and fourth electrodes E3, E4 and which forms a potential barrier BP1 beneath the second electrode E2. Also during this interval of time, the first transfer pulse STl is at the state 1 so that, beneath the first electrode E1, there is a potential VP1 with the same value as beneath the third and fourth electrodes E3, E4, and so that charges Q1, Q2 (shown by hatched lines in the figure) may be stored beneath these electrodes, in being separated by the potential barrier BP1. Thus, the potential well PU1 is formed between the potential barrier BP1, formed beneath the second electrode E2, and a second potential barrier BP2 formed beneath the output gate GS by the application of the potential VGS to this output gate; the value of the potential VGS is such that it generates, beneath the electrode GS, a potential VP3 which is between the potentials VP1 and VP2 and forms the potential barrier BP2.
Again between the instants t8 and t9, at the reading diode 12a with floating potential, namely beneath the N+type doped zone 12, the potential has a value VP4 close to a value VP5 generated beneath the second N+doped zone 13 by the application of the supply voltage VDR. Between these two N+doped zones 12, 13, the control gate GC receives the state 0 (negative potential) of the resetting pulse SRN, this resetting pulse being completed at the instant t8: the result thereof is that the potential beneath the control electrode GC is more negative than beneath the zones 12, 13 and has, for example, a value VP2 so as to form, beneath this control gate, a third potential barrier BP3 that separate the region carried to the potential VP5 (region located beneath the second zone 13) from the potential well PU2 which is formed beneath the first zone 12 and symbolizes the reading diode 12a.
The potential VP4 beneath the first zone 12, namely at the reading diode 12a, is substantially the one applied to the input of the amplifier 16 when no charge has been transferred to the reading diode 12a. This potential VP4 corresponds substantially to the value VST of the output signal, and constitutes the bottom of the potential well PU2 into which the charges get shed; this shedding of the charges modifies the potential applied to the input of the output amplifier 16 and determines the variations in amplitude of the output signal Ss delivered by this amplifier.
Between the potential VP4 of the bottom of the potential well PU2 and the potential VP3 of the second barrier BP2, there is formed a difference in potential DVL which represents the maximum dynamic range available at the reading diode and, consequently, corresponds to the maximum quantity of charges that can be stored in the potential well PU2. Thus, this difference in reading potential DVL should make it possible to collect the maximum charge that can be conveyed by the shift register RD so a not to restrict the dynamic range of the shift register.
FIG. 3b illustrates the shapes of potentials that are generated beneath the electrodes of the structure shown in FIG. 3, between the instants t9 and t10. At the instant t9, the third transfer signal ST3 goes to the state 0, the result of which is that: a fourth potential barrier BP4 is formed beneath the third electrode E3; this fourth potential barrier BP4 extends the first potential barrier BP1, with the effect, firstly, of converting the potential well PU1, shown in FIG. 3a, into a potential well PU1' with a smaller area, formed solely beneath the fourth electrode E4, in such a way that the quantity of charges Q1, which was stored earlier in the potential well PU1 formed beneath the two electrodes E3, E4, should be recovered in the potential well PU1' formed solely beneath the fourth electrode E4.
Under these conditions, when the quantity of charges Q1 is great enough, it may exceed the storage capacity of the potential well PU1', this storage capacity being limited by the height of the second potential barrier BP2, namely by the value of the potential VP3. In this case, where the quantity of charges Q1 is great, a part Q1a spills over the second potential barrier BP2 (formed beneath the output gate Gs) and thus reaches the reading diode. A remaining part Q1b remains stored in the potential well QU1' formed beneath the fourth electrode E4. This transfer, to the reading diode, of the part Q1a of the charges, generates the previously mentioned variation of the output signal Ss which goes from the value VSt to the value VS1; this variation has been cited as being liable to form a major drawback in the case of a reading by differential method.
FIG. 3c illustrates the shapes of the potentials for the structure of FIG. 3, between the instant t10 and the instant tll, shown in FIGS. 2.
At the instant t10, the fourth transfer signal ST4 applied to the fourth electrode E4, goes from the state 1 to the state 0, the result of which is that, beneath the fourth electrode E4, the potential well PU1'(shown in dashes) is replaced by a fifth potential barrier BP5, adjacent to the fourth barrier BP4, in such a way that the quantity of charges QU1b, previously stored beneath the fourth electrode E4 (PU1') is transferred to the reading diode, namely into the potential well PU2. The top of the fifth potential barrier BP5 is formed, for example, by the potential VP2 which also forms the potential barriers BPI, BP3, BP4.
It must be noted that, between the top of the second potential barrier BP2 (that is, of the potential VP3) and the top of the fifth potential barrier BP5 (that is, of the potential VP2) there should be a difference in potential DV1 which is great enough for the charges that were stored beneath the fourth electrode E4 to be transferred to the reading diode before the fifth potential barrier BP5 (beneath the electrode E4) reaches the value VP2. For, if the difference DV1 is too small, some of the charges that were contained beneath the fourth electrode E4 may return backwards, namely towards a potential well PU6 formed beneath the second electrode E2 instead of being transferred to the reading diode, and this leads to a deterioration in the transfer efficiency of the register RD.
In the prior art, the difference in potential DV1 is obtained by significantly increasing the potential VES applied to the output electrode ES (by making this potential even more positive). But this may have the consequence of reducing the reading dynamic range and, in order to preserve a sufficient reading dynamic range, namely a sufficient difference in reading potential DVL, it is then necessary to resort to a disadvantageous solution which consists in increasing (to make it more positive) the voltage VDR which is used to do the resetting of the reading diode. The drawback resulting therefrom is that there is an increase in all the voltages useful for the operation of the output stage: the voltage VES applied to the output electrode, the voltage VDR applied to the second N+doped zone 13 and the voltage VDD for the supply of the output amplifier 16.